1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to receiver circuits for use within integrated circuits for receiving an input signal at an input and converting the input signal to an output signal for use within the integrated circuit.
2. Description of the Prior Art
As process geometries have scaled downward in size and operating voltages have reduced for integrated circuits, there is a growing difference between the interface voltages for integrated circuits and the internal operating voltages. As an example, an interface to the integrated circuit may be defined as operating at 2.7V, whereas the integrated circuit itself may operate at a much lower voltage (e.g. to save power) such as 1V. The input and output circuits are the interface between the external world and the core (interior of the integrated circuit). The core voltage is continuously changing as the technology scales down, but external voltage does not change as frequently, as it is dictated by the common standard and also needs to be backward compatible with earlier generations of circuits and hence the external voltage does not scale down as much with each generation. Such receiver circuits need to operate over a wide voltage range and should not themselves impose a significant signal throughput restriction.
A problem which arises within such receiver circuits when the process size decreases is that oxide layer overstress within NMOS and PMOS devices may occur. For example, this may arise when an NMOS device designed to function within an integrated circuit having a maximum operating voltage of 1.8V but that is subject to an input voltage at its gate having a much higher voltage level, such as 2.7V. This can cause the thin oxide layer to break down and the circuit to malfunction. Voltage tolerant circuits may be provided using zero voltage threshold devices, but such measures require the use of additional masks during manufacture which is a significant disadvantage.
FIG. 12 of the accompanying drawings illustrates one example of a known voltage tolerant receiver circuit. This circuit cannot tolerate voltages of more than 2.7V. Furthermore, in order to ensure correct operation, the delay of the transistor MP1 must be larger than the delay of transistor MP2 so that the pad voltage does not pass to the input node (node 1) of the receiver. As a consequence of this slow transistor within the signal path, the performance of the receiver circuit is degraded and this results in duty cycle distortion.
FIG. 13 of the accompanying drawings illustrates a second known voltage tolerant receiver circuit. This circuit has the disadvantage that for fast slew rates at the input PAD, the node RX_IN is charged to more than 2V and does not discharge to 2V. This creates a reliability problem for the NMOS transistors within the inverter following the RX_IN node. Another problem with this circuit is that when the input voltage PAD is at or above the receiver supply voltage DVDD plus the switching threshold of the transistors, the transmission gate still conducts and so the node RX_IN is charged to more than 2V and once it is charged to this level there is no discharge path.